URL: https://github.com/YosysHQ/yosys
Proper Citation: yosys (RRID:SCR_022549)
Description: Software tool interprets Verilog descriptions of programmable hardware and transforms these into combinations of small look-up tables as provided on FPGAs from Xilinx or Lattice.
Resource Type: data processing software, software resource, software application
Keywords: Verilog descriptions interpretation, Verilog descriptions transformation, small look-up tables
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